Course level

Undergraduate

Faculty

Engineering, Architecture & Information Technology

School

Info Tech & Elec Engineering

Units

2

Duration

One Semester

Class contact

2 Lecture hours, 3 Practical or Laboratory hours

Incompatible

CSSE2000, CSSE3000, CSSE7011, CSSE7410

Prerequisite

CSSE1000 or CSSE2010

Recommended prerequisite

Assessment methods

Practicals, project, research assignment, final exam

Course coordinator

Dr Matthew D'Souza (m.dsouza@uq.edu.au)

Study Abroad

This course is pre-approved for Study Abroad and Exchange students.

Current course offerings

Course offerings Location Mode Course Profile
Semester 2, 2017 St Lucia Internal Course Profile
Semester 2, 2018 St Lucia Internal Profile unavailable

Please Note: Course profiles marked as not available may still be in development.

Course description

The objective of this course is to give the students the theoretical basis & practical skills in modern design of medium size digital systems in various technologies, with a focus on Field Programmable Gate Arrays (FPGAs). The design methodology, systematically introduced & used in the course, is based on simulation & synthesis with hardware description language (VHDL) tools. Topics covered in this course include: conceptual design step from requirements & specification to simulation & synthesis model in VHDL, design of complex controllers with Finite State Machines, design of sequential blocks with Controller-Datapath methodology, issues in design for testability, electrical & timing issues in logic and system design, overview of implementation technologies with emphasis on advances in FPGAs.

Archived offerings

Course offerings Location Mode Course Profile
Semester 2, 2016 St Lucia Internal Course Profile
Semester 2, 2015 St Lucia Internal Course Profile
Semester 2, 2014 St Lucia Internal Course Profile
Semester 2, 2013 St Lucia Internal Course Profile